#define DMA_BASE 0x801A0000
#define DMA_SAR0_MMOFFSET 0x0
#define DMA_DAR0_MMOFFSET 0x8
#define DMA_LLP0_MMOFFSET 0x10
#define DMA_CTL0_MMOFFSET 0x18
#define DMA_SSTAT0_MMOFFSET 0x20
#define DMA_DSTAT0_MMOFFSET 0x28
#define DMA_SSTATAR0_MMOFFSET 0x30
#define DMA_DSTATAR0_MMOFFSET 0x38
#define DMA_CFG0_MMOFFSET 0x40
#define DMA_SAR1_MMOFFSET 0x58
#define DMA_DAR1_MMOFFSET 0x60
#define DMA_LLP1_MMOFFSET 0x68
#define DMA_CTL1_MMOFFSET 0x70
#define DMA_SSTAT1_MMOFFSET 0x78
#define DMA_DSTAT1_MMOFFSET 0x80
#define DMA_SSTATAR1_MMOFFSET 0x88
#define DMA_DSTATAR1_MMOFFSET 0x90
#define DMA_CFG1_MMOFFSET 0x98
#define DMA_SAR2_MMOFFSET 0x0B0
#define DMA_DAR2_MMOFFSET 0x0B8
#define DMA_LLP2_MMOFFSET 0x0C0
#define DMA_CTL2_MMOFFSET 0x0C8
#define DMA_SSTAT2_MMOFFSET 0x0D0
#define DMA_DSTAT2_MMOFFSET 0x0D8
#define DMA_SSTATAR2_MMOFFSET 0x0E0
#define DMA_DSTATAR2_MMOFFSET 0x0E8
#define DMA_CFG2_MMOFFSET 0x0F0
#define DMA_SAR3_MMOFFSET 0x108
#define DMA_DAR3_MMOFFSET 0x110
#define DMA_LLP3_MMOFFSET 0x118
#define DMA_CTL3_MMOFFSET 0x120
#define DMA_SSTAT3_MMOFFSET 0x128
#define DMA_DSTAT3_MMOFFSET 0x130
#define DMA_SSTATAR3_MMOFFSET 0x138
#define DMA_DSTATAR3_MMOFFSET 0x140
#define DMA_CFG3_MMOFFSET 0x148
#define DMA_RAWTFR_MMOFFSET 0x2C0
#define DMA_RAWBLOCK_MMOFFSET 0x2C8
#define DMA_RAWSRCTRAN_MMOFFSET 0x2D0
#define DMA_RAWDSTTRAN_MMOFFSET 0x2D8
#define DMA_RAWERR_MMOFFSET 0x2E0
#define DMA_STATUSTFR_MMOFFSET 0x2E8
#define DMA_STATUSBLOCK_MMOFFSET 0x2F0
#define DMA_STATUSSRCTRAN_MMOFFSET 0x2F8
#define DMA_STATUSDSTTRAN_MMOFFSET 0x300
#define DMA_STATUSERR_MMOFFSET 0x308
#define DMA_MASKTFR_MMOFFSET 0x310
#define DMA_MASKBLOCK_MMOFFSET 0x318
#define DMA_MASKSRCTRAN_MMOFFSET 0x320
#define DMA_MASKDSTTRAN_MMOFFSET 0x328
#define DMA_MASKERR_MMOFFSET 0x330
#define DMA_CLEARTFR_MMOFFSET 0x338
#define DMA_CLEARBLOCK_MMOFFSET 0x340
#define DMA_CLEARSRCTRAN_MMOFFSET 0x348
#define DMA_CLEARDSTTRAN_MMOFFSET 0x350
#define DMA_CLEARERR_MMOFFSET 0x358
#define DMA_STATUSINT_MMOFFSET 0x360
#define DMA_REQSRCREG_MMOFFSET 0x368
#define DMA_REQDSTREG_MMOFFSET 0x370
#define DMA_SGLREQSRCREG_MMOFFSET 0x378
#define DMA_SGLREQDSTREG_MMOFFSET 0x380
#define DMA_LASTSRCREG_MMOFFSET 0x388
#define DMA_LASTDSTREG_MMOFFSET 0x390
#define DMA_DMACFGREG_MMOFFSET 0x398
#define DMA_CHENREG_MMOFFSET 0x3A0
#define DMA_DMAIDREG_MMOFFSET 0x3A8
#define DMA_DMATESTREG_MMOFFSET 0x3B0
#define DMA_DMA_COMP_PARAMS_6_MMOFFSET 0x3C8
#define DMA_DMA_COMP_PARAMS_5_MMOFFSET 0x3D0
#define DMA_DMA_COMP_PARAMS_4_MMOFFSET 0x3D8
#define DMA_DMA_COMP_PARAMS_3_MMOFFSET 0x3E0
#define DMA_DMA_COMP_PARAMS_2_MMOFFSET 0x3E8
#define DMA_DMA_COMP_PARAMS_1_MMOFFSET 0x3F0
#define DMA_DMA_COMPONENT_ID_MMOFFSET 0x3F8

// SAR0 desc:  Source Address Register Channel 0
typedef volatile union {
    struct {
        uint64_t  SAR                  :  32;    //  Current Source Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SAR0_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DAR0 desc:  Destination Address Register Channel 0
typedef volatile union {
    struct {
        uint64_t  DAR                  :  32;    //  Current Destination Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DAR0_t;

// --------------------------------------------------------------------------------------------------------------------------------

// LLP0 desc:  Linked List Pointer Register Channel 0
typedef volatile union {
    struct {
        uint64_t  LMS                  :   2;    //  List Master Select
        uint64_t  LOC                  :  30;    //  Starting Address in Memory
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} LLP0_t;

// --------------------------------------------------------------------------------------------------------------------------------

// CTL0 desc:  Control Register Channel 0
typedef volatile union {
    struct {
        uint64_t  INT_EN               :   1;    //  Interrupt Enable
        uint64_t  DST_TR_WIDTH         :   3;    //  Destination Transfer Width
        uint64_t  SRC_TR_WIDTH         :   3;    //  Source Transfer Width
        uint64_t  DINC                 :   2;    //  Destination Address
                                                 // Increment
        uint64_t  SINC                 :   2;    //  Source Address Increment
        uint64_t  DEST_MSIZE           :   3;    //  Destination Burst
                                                 // Transaction Length
        uint64_t  SRC_MSIZE            :   3;    //  Source Burst Transaction
                                                 // Length
        uint64_t  reserved_SRC_SCATTER_EN :   1;    //  reserved SRC_SCATTER_EN bit
        uint64_t  reserved_DST_SCATTER_EN :   1;    //  reserved DST_SCATTER_EN bit
        uint64_t  RSVD_0               :   1;    // Nebulon auto filled RSVD [19:19]
        uint64_t  TT_FC                :   3;    //  Transfer Type and Flow
                                                 // Control
        uint64_t  DMS                  :   2;    //  Desination Master Select
        uint64_t  SMS                  :   2;    //  Source Master Select
        uint64_t  LLP_DST_EN           :   1;    //  source block chaining
                                                 // enabled bit
        uint64_t  LLP_SRC_EN           :   1;    //  source block chaining
                                                 // enabled bit
        uint64_t  reserved_a           :   3;    //  reserved bits
        uint64_t  BLOCK_TS             :  12;    //  Block Transfer Size
        uint64_t  DONE                 :   1;    //  Done bit
        uint64_t  reserved             :  19;    //  reserved bits

    }                                field;
    uint64_t                         val;
} CTL0_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SSTAT0 desc:  Source Status Register Channel 0
typedef volatile union {
    struct {
        uint64_t  SSTAT                :  32;    //  Source Status
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SSTAT0_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DSTAT0 desc:  Destination Status Register Channel 0
typedef volatile union {
    struct {
        uint64_t  DSTAT                :  32;    //  Destination Status
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DSTAT0_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SSTATAR0 desc:  Source Status Address Register Channel 0
typedef volatile union {
    struct {
        uint64_t  SSTAT                :  32;    //  Source Status Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SSTATAR0_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DSTATAR0 desc:  Destination Status Address Register Channel 0
typedef volatile union {
    struct {
        uint64_t  DSTATAR              :  32;    //  Destination Status Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DSTATAR0_t;

// --------------------------------------------------------------------------------------------------------------------------------

// CFG0 desc:  Configuration Register Channel 0
typedef volatile union {
    struct {
        uint64_t  RSVD_0               : 5;    // Nebulon auto filled RSVD [0:4]
        uint64_t  CH_PRIOR             :   3;    //  Channel priority
        uint64_t  CH_SUSP              :   1;    //  Channel suspend
        uint64_t  FIFO_EMPTY           :   1;    //  Destination Software or
                                                 // Hardware Handshaking Select
        uint64_t  HS_SEL_DST           :   1;    //  Destination Software or
                                                 // Hardware Handshaking Select
        uint64_t  HS_SEL_SRC           :   1;    //  Source Software or Hardware
                                                 // Handshaking Select
        uint64_t  RSVD_1               :   6;    // Nebulon auto filled RSVD [17:12]
        uint64_t  DST_HS_POL           :   1;    //  Destination Handshaking
                                                 // Interface Polarity
        uint64_t  SRC_HS_POL           :   1;    //  Source Handshaking Interface
                                                 // Polarity
        uint64_t  MAX_ABRST            :  10;    //  Maximum AMBA Burst Length
        uint64_t  RSVD_2               :   2;    // Nebulon auto filled RSVD [31:30]
        uint64_t  FCMODE               :   1;    //  Flow Control mode
        uint64_t  FIFO_MODE            :   1;    //  FIFO mode select
        uint64_t  PROTCTL              :   3;    //  protection control
        uint64_t  RSVD_3               :   2;    // Nebulon auto filled RSVD [38:37]
        uint64_t  SRC_PER              :   2;    //  Source Peripheral selection
        uint64_t  RSVD_4               :   2;    // Nebulon auto filled RSVD [42:41]
        uint64_t  DEST_PER             :   2;    //  Destination Peripheral
                                                 // selection
        uint64_t  reserved             :  19;    //  reserved bits

    }                                field;
    uint64_t                         val;
} CFG0_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SAR1 desc:  Source Address Register Channel 1
typedef volatile union {
    struct {
        uint64_t  SAR                  :  32;    //  Current Source Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SAR1_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DAR1 desc:  Destination Address Register Channel 1
typedef volatile union {
    struct {
        uint64_t  DAR                  :  32;    //  Current Destination Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DAR1_t;

// --------------------------------------------------------------------------------------------------------------------------------

// LLP1 desc:  Linked List Pointer Register Channel 1
typedef volatile union {
    struct {
        uint64_t  LMS                  :   2;    //  List Master Select
        uint64_t  LOC                  :  30;    //  Starting Address in Memory
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} LLP1_t;

// --------------------------------------------------------------------------------------------------------------------------------

// CTL1 desc:  Control Register Channel 1
typedef volatile union {
    struct {
        uint64_t  INT_EN               :   1;    //  Interrupt Enable
        uint64_t  DST_TR_WIDTH         :   3;    //  Destination Transfer Width
        uint64_t  SRC_TR_WIDTH         :   3;    //  Source Transfer Width
        uint64_t  DINC                 :   2;    //  Destination Address
                                                 // Increment
        uint64_t  SINC                 :   2;    //  Source Address Increment
        uint64_t  DEST_MSIZE           :   3;    //  Destination Burst
                                                 // Transaction Length
        uint64_t  SRC_MSIZE            :   3;    //  Source Burst Transaction
                                                 // Length
        uint64_t  reserved_SRC_SCATTER_EN :   1;    //  reserved SRC_SCATTER_EN bit
        uint64_t  reserved_DST_SCATTER_EN :   1;    //  reserved DST_SCATTER_EN bit
        uint64_t  RSVD_0               :   1;    // Nebulon auto filled RSVD [19:19]
        uint64_t  TT_FC                :   3;    //  Transfer Type and Flow
                                                 // Control
        uint64_t  DMS                  :   2;    //  Desination Master Select
        uint64_t  SMS                  :   2;    //  Source Master Select
        uint64_t  LLP_DST_EN           :   1;    //  source block chaining
                                                 // enabled bit
        uint64_t  LLP_SRC_EN           :   1;    //  source block chaining
                                                 // enabled bit
        uint64_t  reserved_a           :   3;    //  reserved bits
        uint64_t  BLOCK_TS             :  12;    //  Block Transfer Size
        uint64_t  DONE                 :   1;    //  Done bit
        uint64_t  reserved             :  19;    //  reserved bits

    }                                field;
    uint64_t                         val;
} CTL1_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SSTAT1 desc:  Source Status Register Channel 1
typedef volatile union {
    struct {
        uint64_t  SSTAT                :  32;    //  Source Status
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SSTAT1_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DSTAT1 desc:  Destination Status Register Channel 1
typedef volatile union {
    struct {
        uint64_t  DSTAT                :  32;    //  Destination Status
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DSTAT1_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SSTATAR1 desc:  Source Status Address Register Channel 1
typedef volatile union {
    struct {
        uint64_t  SSTAT                :  32;    //  Source Status Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SSTATAR1_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DSTATAR1 desc:  Destination Status Address Register Channel 1
typedef volatile union {
    struct {
        uint64_t  DSTATAR              :  32;    //  Destination Status Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DSTATAR1_t;

// --------------------------------------------------------------------------------------------------------------------------------

// CFG1 desc:  Configuration Register Channel 1
typedef volatile union {
    struct {
        uint64_t  RSVD_0               : 5;    // Nebulon auto filled RSVD [0:4]
        uint64_t  CH_PRIOR             :   3;    //  Channel priority
        uint64_t  CH_SUSP              :   1;    //  Channel suspend
        uint64_t  FIFO_EMPTY           :   1;    //  Destination Software or
                                                 // Hardware Handshaking Select
        uint64_t  HS_SEL_DST           :   1;    //  Destination Software or
                                                 // Hardware Handshaking Select
        uint64_t  HS_SEL_SRC           :   1;    //  Source Software or Hardware
                                                 // Handshaking Select
        uint64_t  RSVD_1               :   6;    // Nebulon auto filled RSVD [17:12]
        uint64_t  DST_HS_POL           :   1;    //  Destination Handshaking
                                                 // Interface Polarity
        uint64_t  SRC_HS_POL           :   1;    //  Source Handshaking Interface
                                                 // Polarity
        uint64_t  MAX_ABRST            :  10;    //  Maximum AMBA Burst Length
        uint64_t  RSVD_2               :   2;    // Nebulon auto filled RSVD [31:30]
        uint64_t  FCMODE               :   1;    //  Flow Control mode
        uint64_t  FIFO_MODE            :   1;    //  FIFO mode select
        uint64_t  PROTCTL              :   3;    //  protection control
        uint64_t  RSVD_3               :   2;    // Nebulon auto filled RSVD [38:37]
        uint64_t  SRC_PER              :   2;    //  Source Peripheral selection
        uint64_t  RSVD_4               :   2;    // Nebulon auto filled RSVD [42:41]
        uint64_t  DEST_PER             :   2;    //  Destination Peripheral
                                                 // selection
        uint64_t  reserved             :  19;    //  reserved bits

    }                                field;
    uint64_t                         val;
} CFG1_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SAR2 desc:  Source Address Register Channel 2
typedef volatile union {
    struct {
        uint64_t  SAR                  :  32;    //  Current Source Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SAR2_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DAR2 desc:  Destination Address Register Channel 2
typedef volatile union {
    struct {
        uint64_t  DAR                  :  32;    //  Current Destination Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DAR2_t;

// --------------------------------------------------------------------------------------------------------------------------------

// LLP2 desc:  Linked List Pointer Register Channel 2
typedef volatile union {
    struct {
        uint64_t  LMS                  :   2;    //  List Master Select
        uint64_t  LOC                  :  30;    //  Starting Address in Memory
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} LLP2_t;

// --------------------------------------------------------------------------------------------------------------------------------

// CTL2 desc:  Control Register Channel 2
typedef volatile union {
    struct {
        uint64_t  INT_EN               :   1;    //  Interrupt Enable
        uint64_t  DST_TR_WIDTH         :   3;    //  Destination Transfer Width
        uint64_t  SRC_TR_WIDTH         :   3;    //  Source Transfer Width
        uint64_t  DINC                 :   2;    //  Destination Address
                                                 // Increment
        uint64_t  SINC                 :   2;    //  Source Address Increment
        uint64_t  DEST_MSIZE           :   3;    //  Destination Burst
                                                 // Transaction Length
        uint64_t  SRC_MSIZE            :   3;    //  Source Burst Transaction
                                                 // Length
        uint64_t  reserved_SRC_SCATTER_EN :   1;    //  reserved SRC_SCATTER_EN bit
        uint64_t  reserved_DST_SCATTER_EN :   1;    //  reserved DST_SCATTER_EN bit
        uint64_t  RSVD_0               :   1;    // Nebulon auto filled RSVD [19:19]
        uint64_t  TT_FC                :   3;    //  Transfer Type and Flow
                                                 // Control
        uint64_t  DMS                  :   2;    //  Desination Master Select
        uint64_t  SMS                  :   2;    //  Source Master Select
        uint64_t  LLP_DST_EN           :   1;    //  source block chaining
                                                 // enabled bit
        uint64_t  LLP_SRC_EN           :   1;    //  source block chaining
                                                 // enabled bit
        uint64_t  reserved_a           :   3;    //  reserved bits
        uint64_t  BLOCK_TS             :  12;    //  Block Transfer Size
        uint64_t  DONE                 :   1;    //  Done bit
        uint64_t  reserved             :  19;    //  reserved bits

    }                                field;
    uint64_t                         val;
} CTL2_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SSTAT2 desc:  Source Status Register Channel 2
typedef volatile union {
    struct {
        uint64_t  SSTAT                :  32;    //  Source Status
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SSTAT2_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DSTAT2 desc:  Destination Status Register Channel 2
typedef volatile union {
    struct {
        uint64_t  DSTAT                :  32;    //  Destination Status
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DSTAT2_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SSTATAR2 desc:  Source Status Address Register Channel 2
typedef volatile union {
    struct {
        uint64_t  SSTAT                :  32;    //  Source Status Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SSTATAR2_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DSTATAR2 desc:  Destination Status Address Register Channel 2
typedef volatile union {
    struct {
        uint64_t  DSTATAR              :  32;    //  Destination Status Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DSTATAR2_t;

// --------------------------------------------------------------------------------------------------------------------------------

// CFG2 desc:  Configuration Register Channel 2
typedef volatile union {
    struct {
        uint64_t  RSVD_0               : 5;    // Nebulon auto filled RSVD [0:4]
        uint64_t  CH_PRIOR             :   3;    //  Channel priority
        uint64_t  CH_SUSP              :   1;    //  Channel suspend
        uint64_t  FIFO_EMPTY           :   1;    //  Destination Software or
                                                 // Hardware Handshaking Select
        uint64_t  HS_SEL_DST           :   1;    //  Destination Software or
                                                 // Hardware Handshaking Select
        uint64_t  HS_SEL_SRC           :   1;    //  Source Software or Hardware
                                                 // Handshaking Select
        uint64_t  RSVD_1               :   6;    // Nebulon auto filled RSVD [17:12]
        uint64_t  DST_HS_POL           :   1;    //  Destination Handshaking
                                                 // Interface Polarity
        uint64_t  SRC_HS_POL           :   1;    //  Source Handshaking Interface
                                                 // Polarity
        uint64_t  MAX_ABRST            :  10;    //  Maximum AMBA Burst Length
        uint64_t  RSVD_2               :   2;    // Nebulon auto filled RSVD [31:30]
        uint64_t  FCMODE               :   1;    //  Flow Control mode
        uint64_t  FIFO_MODE            :   1;    //  FIFO mode select
        uint64_t  PROTCTL              :   3;    //  protection control
        uint64_t  RSVD_3               :   2;    // Nebulon auto filled RSVD [38:37]
        uint64_t  SRC_PER              :   2;    //  Source Peripheral selection
        uint64_t  RSVD_4               :   2;    // Nebulon auto filled RSVD [42:41]
        uint64_t  DEST_PER             :   2;    //  Destination Peripheral
                                                 // selection
        uint64_t  reserved             :  19;    //  reserved bits

    }                                field;
    uint64_t                         val;
} CFG2_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SAR3 desc:  Source Address Register Channel 3
typedef volatile union {
    struct {
        uint64_t  SAR                  :  32;    //  Current Source Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SAR3_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DAR3 desc:  Destination Address Register Channel 3
typedef volatile union {
    struct {
        uint64_t  DAR                  :  32;    //  Current Destination Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DAR3_t;

// --------------------------------------------------------------------------------------------------------------------------------

// LLP3 desc:  Linked List Pointer Register Channel 3
typedef volatile union {
    struct {
        uint64_t  LMS                  :   2;    //  List Master Select
        uint64_t  LOC                  :  30;    //  Starting Address in Memory
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} LLP3_t;

// --------------------------------------------------------------------------------------------------------------------------------

// CTL3 desc:  Control Register Channel 3
typedef volatile union {
    struct {
        uint64_t  INT_EN               :   1;    //  Interrupt Enable
        uint64_t  DST_TR_WIDTH         :   3;    //  Destination Transfer Width
        uint64_t  SRC_TR_WIDTH         :   3;    //  Source Transfer Width
        uint64_t  DINC                 :   2;    //  Destination Address
                                                 // Increment
        uint64_t  SINC                 :   2;    //  Source Address Increment
        uint64_t  DEST_MSIZE           :   3;    //  Destination Burst
                                                 // Transaction Length
        uint64_t  SRC_MSIZE            :   3;    //  Source Burst Transaction
                                                 // Length
        uint64_t  reserved_SRC_SCATTER_EN :   1;    //  reserved SRC_SCATTER_EN bit
        uint64_t  reserved_DST_SCATTER_EN :   1;    //  reserved DST_SCATTER_EN bit
        uint64_t  RSVD_0               :   1;    // Nebulon auto filled RSVD [19:19]
        uint64_t  TT_FC                :   3;    //  Transfer Type and Flow
                                                 // Control
        uint64_t  DMS                  :   2;    //  Desination Master Select
        uint64_t  SMS                  :   2;    //  Source Master Select
        uint64_t  LLP_DST_EN           :   1;    //  source block chaining
                                                 // enabled bit
        uint64_t  LLP_SRC_EN           :   1;    //  source block chaining
                                                 // enabled bit
        uint64_t  reserved_a           :   3;    //  reserved bits
        uint64_t  BLOCK_TS             :  12;    //  Block Transfer Size
        uint64_t  DONE                 :   1;    //  Done bit
        uint64_t  reserved             :  19;    //  reserved bits

    }                                field;
    uint64_t                         val;
} CTL3_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SSTAT3 desc:  Source Status Register Channel 3
typedef volatile union {
    struct {
        uint64_t  SSTAT                :  32;    //  Source Status
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SSTAT3_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DSTAT3 desc:  Destination Status Register Channel 3
typedef volatile union {
    struct {
        uint64_t  DSTAT                :  32;    //  Destination Status
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DSTAT3_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SSTATAR3 desc:  Source Status Address Register Channel 3
typedef volatile union {
    struct {
        uint64_t  SSTAT                :  32;    //  Source Status Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SSTATAR3_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DSTATAR3 desc:  Destination Status Address Register Channel 3
typedef volatile union {
    struct {
        uint64_t  DSTATAR              :  32;    //  Destination Status Address
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DSTATAR3_t;

// --------------------------------------------------------------------------------------------------------------------------------

// CFG3 desc:  Configuration Register Channel 3
typedef volatile union {
    struct {
        uint64_t  RSVD_0               : 5;    // Nebulon auto filled RSVD [0:4]
        uint64_t  CH_PRIOR             :   3;    //  Channel priority
        uint64_t  CH_SUSP              :   1;    //  Channel suspend
        uint64_t  FIFO_EMPTY           :   1;    //  Destination Software or
                                                 // Hardware Handshaking Select
        uint64_t  HS_SEL_DST           :   1;    //  Destination Software or
                                                 // Hardware Handshaking Select
        uint64_t  HS_SEL_SRC           :   1;    //  Source Software or Hardware
                                                 // Handshaking Select
        uint64_t  RSVD_1               :   6;    // Nebulon auto filled RSVD [17:12]
        uint64_t  DST_HS_POL           :   1;    //  Destination Handshaking
                                                 // Interface Polarity
        uint64_t  SRC_HS_POL           :   1;    //  Source Handshaking Interface
                                                 // Polarity
        uint64_t  MAX_ABRST            :  10;    //  Maximum AMBA Burst Length
        uint64_t  RSVD_2               :   2;    // Nebulon auto filled RSVD [31:30]
        uint64_t  FCMODE               :   1;    //  Flow Control mode
        uint64_t  FIFO_MODE            :   1;    //  FIFO mode select
        uint64_t  PROTCTL              :   3;    //  protection control
        uint64_t  RSVD_3               :   2;    // Nebulon auto filled RSVD [38:37]
        uint64_t  SRC_PER              :   2;    //  Source Peripheral selection
        uint64_t  RSVD_4               :   2;    // Nebulon auto filled RSVD [42:41]
        uint64_t  DEST_PER             :   2;    //  Destination Peripheral
                                                 // selection
        uint64_t  reserved             :  19;    //  reserved bits

    }                                field;
    uint64_t                         val;
} CFG3_t;

// --------------------------------------------------------------------------------------------------------------------------------

// RawTfr desc:  Raw Transfer Interrupt Register
typedef volatile union {
    struct {
        uint64_t  RAW                  :   4;    //  Raw Transfer Interrupt
                                                 // Status
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} RawTfr_t;

// --------------------------------------------------------------------------------------------------------------------------------

// RawBlock desc:  Raw Block Interrupt Register
typedef volatile union {
    struct {
        uint64_t  RAW                  :   4;    //  Raw Block Interrupt Status
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} RawBlock_t;

// --------------------------------------------------------------------------------------------------------------------------------

// RawSrcTran desc:  Raw Source Transaction Complete Register
typedef volatile union {
    struct {
        uint64_t  RAW                  :   4;    //  Raw Source Transaction
                                                 // Complete Status
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} RawSrcTran_t;

// --------------------------------------------------------------------------------------------------------------------------------

// RawDstTran desc:  Raw Destination Transaction Complete Register
typedef volatile union {
    struct {
        uint64_t  RAW                  :   4;    //  Raw Destination Transaction
                                                 // Complete Status
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} RawDstTran_t;

// --------------------------------------------------------------------------------------------------------------------------------

// RawErr desc:  Raw Error Status Register
typedef volatile union {
    struct {
        uint64_t  RAW                  :   4;    //  Raw Error Status
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} RawErr_t;

// --------------------------------------------------------------------------------------------------------------------------------

// StatusTfr desc:  Status Transfer Interrupt Register
typedef volatile union {
    struct {
        uint64_t  STATUS               :   4;    //  Status Transfer Interrupt
                                                 // Status
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} StatusTfr_t;

// --------------------------------------------------------------------------------------------------------------------------------

// StatusBlock desc:  Status Block Interrupt Register
typedef volatile union {
    struct {
        uint64_t  STATUS               :   4;    //  Status Block Interrupt
                                                 // Status
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} StatusBlock_t;

// --------------------------------------------------------------------------------------------------------------------------------

// StatusSrcTran desc:  Status Source Transaction Complete Register
typedef volatile union {
    struct {
        uint64_t  STATUS               :   4;    //  Status Source Transaction
                                                 // Complete Status
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} StatusSrcTran_t;

// --------------------------------------------------------------------------------------------------------------------------------

// StatusDstTran desc:  Status Destination Transaction Complete Register
typedef volatile union {
    struct {
        uint64_t  STATUS               :   4;    //  Status Destination
                                                 // Transaction Complete Status
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} StatusDstTran_t;

// --------------------------------------------------------------------------------------------------------------------------------

// StatusErr desc:  Status Error Status Register
typedef volatile union {
    struct {
        uint64_t  STATUS               :   4;    //  Status Error Status
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} StatusErr_t;

// --------------------------------------------------------------------------------------------------------------------------------

// MaskTfr desc:  Mask Transfer Interrupt Register
typedef volatile union {
    struct {
        uint64_t  INT_MASK             :   4;    //  Interrupt Mask
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  INT_MASK_WE          :   4;    //  Interrupt Mask Write Enable
        uint64_t  reserved             :  52;    //  reserved bits

    }                                field;
    uint64_t                         val;
} MaskTfr_t;

// --------------------------------------------------------------------------------------------------------------------------------

// MaskBlock desc:  Mask Block Interrupt Register
typedef volatile union {
    struct {
        uint64_t  INT_MASK             :   4;    //  Interrupt Mask
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  INT_MASK_WE          :   4;    //  Interrupt Mask Write Enable
        uint64_t  reserved             :  52;    //  reserved bits

    }                                field;
    uint64_t                         val;
} MaskBlock_t;

// --------------------------------------------------------------------------------------------------------------------------------

// MaskSrcTran desc:  Mask Source Transaction Complete Register
typedef volatile union {
    struct {
        uint64_t  INT_MASK             :   4;    //  Interrupt Mask
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  INT_MASK_WE          :   4;    //  Interrupt Mask Write Enable
        uint64_t  reserved             :  52;    //  reserved bits

    }                                field;
    uint64_t                         val;
} MaskSrcTran_t;

// --------------------------------------------------------------------------------------------------------------------------------

// MaskDstTran desc:  Mask Destination Transaction Complete Register
typedef volatile union {
    struct {
        uint64_t  INT_MASK             :   4;    //  Interrupt Mask
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  INT_MASK_WE          :   4;    //  Interrupt Mask Write Enable
        uint64_t  reserved             :  52;    //  reserved bits

    }                                field;
    uint64_t                         val;
} MaskDstTran_t;

// --------------------------------------------------------------------------------------------------------------------------------

// MaskErr desc:  Mask Error Mask Register
typedef volatile union {
    struct {
        uint64_t  INT_MASK             :   4;    //  Interrupt Mask
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  INT_MASK_WE          :   4;    //  Interrupt Mask Write Enable
        uint64_t  reserved             :  52;    //  reserved bits

    }                                field;
    uint64_t                         val;
} MaskErr_t;

// --------------------------------------------------------------------------------------------------------------------------------

// ClearTfr desc:  Clear Transfer Interrupt Register
typedef volatile union {
    struct {
        uint64_t  CLEAR                :   4;    //  Clear Transfer Interrupt
                                                 // Clear
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} ClearTfr_t;

// --------------------------------------------------------------------------------------------------------------------------------

// ClearBlock desc:  Clear Block Interrupt Register
typedef volatile union {
    struct {
        uint64_t  CLEAR                :   4;    //  Clear Block Interrupt Clear
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} ClearBlock_t;

// --------------------------------------------------------------------------------------------------------------------------------

// ClearSrcTran desc:  Clear Source Transaction Complete Register
typedef volatile union {
    struct {
        uint64_t  CLEAR                :   4;    //  Clear Source Transaction
                                                 // Complete Clear
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} ClearSrcTran_t;

// --------------------------------------------------------------------------------------------------------------------------------

// ClearDstTran desc:  Clear Destination Transaction Complete Register
typedef volatile union {
    struct {
        uint64_t  CLEAR                :   4;    //  Clear Destination
                                                 // Transaction Complete Clear
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} ClearDstTran_t;

// --------------------------------------------------------------------------------------------------------------------------------

// ClearErr desc:  Clear Error Clear Register
typedef volatile union {
    struct {
        uint64_t  CLEAR                :   4;    //  Clear Error Clear
        uint64_t  reserved             :  60;    //  reserved bits

    }                                field;
    uint64_t                         val;
} ClearErr_t;

// --------------------------------------------------------------------------------------------------------------------------------

// Statusint desc:  Combined Interrupt Status Register
typedef volatile union {
    struct {
        uint64_t  TFR                  :   1;    //  OR of the contents of
                                                 // StatusTfr register
        uint64_t  BLOCK                :   1;    //  OR of the contents of
                                                 // StatusBlock register
        uint64_t  SRCT                 :   1;    //  OR of the contents of
                                                 // StatusSrc register
        uint64_t  DSTT                 :   1;    //  OR of the contents of
                                                 // StatusDst register
        uint64_t  ERR                  :   1;    //  OR of the contents of
                                                 // StatusErr register
        uint64_t  reserved             :  59;    //  reserved bits

    }                                field;
    uint64_t                         val;
} Statusint_t;

// --------------------------------------------------------------------------------------------------------------------------------

// ReqSrcReg desc:  Source Software Transaction Request Register
typedef volatile union {
    struct {
        uint64_t  SRC_REQ              :   4;    //  Source request
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  SRC_REQ_WE           :   4;    //  Source request write enable
        uint64_t  reserved             :  52;    //  reserved bits

    }                                field;
    uint64_t                         val;
} ReqSrcReg_t;

// --------------------------------------------------------------------------------------------------------------------------------

// ReqDstReg desc:  Destination Software Transaction Request Register
typedef volatile union {
    struct {
        uint64_t  DST_REQ              :   4;    //  Destination request
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  DST_REQ_WE           :   4;    //  Destination request write
                                                 // enable
        uint64_t  reserved             :  52;    //  reserved bits

    }                                field;
    uint64_t                         val;
} ReqDstReg_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SglReqSrcReg desc:  Single Source Transaction Request Register
typedef volatile union {
    struct {
        uint64_t  SRC_SGLREQ           :   4;    //  Single Source request
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  SRC_SGLREQ_WE        :   4;    //  Single Source request write
                                                 // enable
        uint64_t  reserved             :  52;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SglReqSrcReg_t;

// --------------------------------------------------------------------------------------------------------------------------------

// SglReqDstReg desc:  Single Destination Transaction Request Register
typedef volatile union {
    struct {
        uint64_t  DST_SGLREQ           :   4;    //  Single Destination request
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  DST_SGLREQ_WE        :   4;    //  Single Destination request
                                                 // write enable
        uint64_t  reserved             :  52;    //  reserved bits

    }                                field;
    uint64_t                         val;
} SglReqDstReg_t;

// --------------------------------------------------------------------------------------------------------------------------------

// LastSrcReg desc:  Last Source Transaction Request Register
typedef volatile union {
    struct {
        uint64_t  LSTSRC               :   4;    //  Source last transaction
                                                 // request
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  LSTSRC_WE            :   4;    //  Source last transaction
                                                 // request write enable
        uint64_t  reserved             :  52;    //  reserved bits

    }                                field;
    uint64_t                         val;
} LastSrcReg_t;

// --------------------------------------------------------------------------------------------------------------------------------

// LastDstReg desc:  Last Destination Transaction Request Register
typedef volatile union {
    struct {
        uint64_t  DST_SGLREQ           :   4;    //  Single Destination request
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  DST_SGLREQ_WE        :   4;    //  Single Destination request
                                                 // write enable
        uint64_t  reserved             :  52;    //  reserved bits

    }                                field;
    uint64_t                         val;
} LastDstReg_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DmaCfgReg desc:  DMA Configuration Register
typedef volatile union {
    struct {
        uint64_t  DMA_EN               :   1;    //  DMA enable bit
        uint64_t  reserved             :  63;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DmaCfgReg_t;

// --------------------------------------------------------------------------------------------------------------------------------

// ChEnReg desc:  Last Destination Transaction Request Register
typedef volatile union {
    struct {
        uint64_t  CH_EN                :   4;    //  Channel enable
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  CH_EN_WE             :   4;    //  Channel enable write enable
        uint64_t  reserved             :  52;    //  reserved bits

    }                                field;
    uint64_t                         val;
} ChEnReg_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DmaIdReg desc:  DMA ID Register
typedef volatile union {
    struct {
        uint64_t  DMA_ID               :  32;    //  Hardcoded DW_ahb_dmac
                                                 // Peripheral ID
        uint64_t  reserved             :  32;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DmaIdReg_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DmaTestReg desc:  DMA Configuration Register
typedef volatile union {
    struct {
        uint64_t  TEST_SLV_IF          :   1;    //  Slave interface test mode
        uint64_t  reserved             :  63;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DmaTestReg_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DMA_COMP_PARAMS_6 desc:  Component Parameters Register 6
typedef volatile union {
    struct {
        uint64_t  reserved_a           :  32;    //  reserved bits
        uint64_t  CH7_DTW              :   3;    //  see name
        uint64_t  CH7_STW              :   3;    //  see name
        uint64_t  CH7_STAT_DST         :   1;    //  see name
        uint64_t  CH7_STAT_SRC         :   1;    //  see name
        uint64_t  CH7_DST_SCA_EN       :   1;    //  see name
        uint64_t  CH7_SRC_GAT_EN       :   1;    //  see name
        uint64_t  CH7_LOCK_EN          :   1;    //  see name
        uint64_t  CH7_MULTI_BLK_EN     :   1;    //  see name
        uint64_t  CH7_CTL_WB_EN        :   1;    //  see name
        uint64_t  CH7_HC_LLP           :   1;    //  see name
        uint64_t  CH7_FC               :   2;    //  see name
        uint64_t  CH7_MAX_MULT_SIZE    :   3;    //  see name
        uint64_t  CH7_DMS              :   3;    //  see name
        uint64_t  CH7_LMS              :   3;    //  see name
        uint64_t  CH7_SMS              :   3;    //  see name
        uint64_t  CH7_FIFO_DEPTH       :   3;    //  see name
        uint64_t  reserved             :   1;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DMA_COMP_PARAMS_6_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DMA_COMP_PARAMS_5 desc:  Component Parameters Register 5
typedef volatile union {
    struct {
        uint64_t  CH6_DTW              :   3;    //  see name
        uint64_t  CH6_STW              :   3;    //  see name
        uint64_t  CH6_STAT_DST         :   1;    //  see name
        uint64_t  CH6_STAT_SRC         :   1;    //  see name
        uint64_t  CH6_DST_SCA_EN       :   1;    //  see name
        uint64_t  CH6_SRC_GAT_EN       :   1;    //  see name
        uint64_t  CH6_LOCK_EN          :   1;    //  see name
        uint64_t  CH6_MULTI_BLK_EN     :   1;    //  see name
        uint64_t  CH6_CTL_WB_EN        :   1;    //  see name
        uint64_t  CH6_HC_LLP           :   1;    //  see name
        uint64_t  CH6_FC               :   2;    //  see name
        uint64_t  CH6_MAX_MULT_SIZE    :   3;    //  see name
        uint64_t  CH6_DMS              :   3;    //  see name
        uint64_t  CH6_LMS              :   3;    //  see name
        uint64_t  CH6_SMS              :   3;    //  see name
        uint64_t  CH6_FIFO_DEPTH       :   3;    //  see name
        uint64_t  reserved_a           :   1;    //  reserved bits
        uint64_t  CH5_DTW              :   3;    //  see name
        uint64_t  CH5_STW              :   3;    //  see name
        uint64_t  CH5_STAT_DST         :   1;    //  see name
        uint64_t  CH5_STAT_SRC         :   1;    //  see name
        uint64_t  CH5_DST_SCA_EN       :   1;    //  see name
        uint64_t  CH5_SRC_GAT_EN       :   1;    //  see name
        uint64_t  CH5_LOCK_EN          :   1;    //  see name
        uint64_t  CH5_MULTI_BLK_EN     :   1;    //  see name
        uint64_t  CH5_CTL_WB_EN        :   1;    //  see name
        uint64_t  CH5_HC_LLP           :   1;    //  see name
        uint64_t  CH5_FC               :   2;    //  see name
        uint64_t  CH5_MAX_MULT_SIZE    :   3;    //  see name
        uint64_t  CH5_DMS              :   3;    //  see name
        uint64_t  CH5_LMS              :   3;    //  see name
        uint64_t  CH5_SMS              :   3;    //  see name
        uint64_t  CH5_FIFO_DEPTH       :   3;    //  see name
        uint64_t  reserved             :   1;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DMA_COMP_PARAMS_5_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DMA_COMP_PARAMS_4 desc:  Component Parameters Register 4
typedef volatile union {
    struct {
        uint64_t  CH4_DTW              :   3;    //  see name
        uint64_t  CH4_STW              :   3;    //  see name
        uint64_t  CH4_STAT_DST         :   1;    //  see name
        uint64_t  CH4_STAT_SRC         :   1;    //  see name
        uint64_t  CH4_DST_SCA_EN       :   1;    //  see name
        uint64_t  CH4_SRC_GAT_EN       :   1;    //  see name
        uint64_t  CH4_LOCK_EN          :   1;    //  see name
        uint64_t  CH4_MULTI_BLK_EN     :   1;    //  see name
        uint64_t  CH4_CTL_WB_EN        :   1;    //  see name
        uint64_t  CH4_HC_LLP           :   1;    //  see name
        uint64_t  CH4_FC               :   2;    //  see name
        uint64_t  CH4_MAX_MULT_SIZE    :   3;    //  see name
        uint64_t  CH4_DMS              :   3;    //  see name
        uint64_t  CH4_LMS              :   3;    //  see name
        uint64_t  CH4_SMS              :   3;    //  see name
        uint64_t  CH4_FIFO_DEPTH       :   3;    //  see name
        uint64_t  reserved_a           :   1;    //  reserved bits
        uint64_t  CH3_DTW              :   3;    //  see name
        uint64_t  CH3_STW              :   3;    //  see name
        uint64_t  CH3_STAT_DST         :   1;    //  see name
        uint64_t  CH3_STAT_SRC         :   1;    //  see name
        uint64_t  CH3_DST_SCA_EN       :   1;    //  see name
        uint64_t  CH3_SRC_GAT_EN       :   1;    //  see name
        uint64_t  CH3_LOCK_EN          :   1;    //  see name
        uint64_t  CH3_MULTI_BLK_EN     :   1;    //  see name
        uint64_t  CH3_CTL_WB_EN        :   1;    //  see name
        uint64_t  CH3_HC_LLP           :   1;    //  see name
        uint64_t  CH3_FC               :   2;    //  see name
        uint64_t  CH3_MAX_MULT_SIZE    :   3;    //  see name
        uint64_t  CH3_DMS              :   3;    //  see name
        uint64_t  CH3_LMS              :   3;    //  see name
        uint64_t  CH3_SMS              :   3;    //  see name
        uint64_t  CH3_FIFO_DEPTH       :   3;    //  see name
        uint64_t  reserved             :   1;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DMA_COMP_PARAMS_4_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DMA_COMP_PARAMS_3 desc:  Component Parameters Register 3
typedef volatile union {
    struct {
        uint64_t  CH2_DTW              :   3;    //  see name
        uint64_t  CH2_STW              :   3;    //  see name
        uint64_t  CH2_STAT_DST         :   1;    //  see name
        uint64_t  CH2_STAT_SRC         :   1;    //  see name
        uint64_t  CH2_DST_SCA_EN       :   1;    //  see name
        uint64_t  CH2_SRC_GAT_EN       :   1;    //  see name
        uint64_t  CH2_LOCK_EN          :   1;    //  see name
        uint64_t  CH2_MULTI_BLK_EN     :   1;    //  see name
        uint64_t  CH2_CTL_WB_EN        :   1;    //  see name
        uint64_t  CH2_HC_LLP           :   1;    //  see name
        uint64_t  CH2_FC               :   2;    //  see name
        uint64_t  CH2_MAX_MULT_SIZE    :   3;    //  see name
        uint64_t  CH2_DMS              :   3;    //  see name
        uint64_t  CH2_LMS              :   3;    //  see name
        uint64_t  CH2_SMS              :   3;    //  see name
        uint64_t  CH2_FIFO_DEPTH       :   3;    //  see name
        uint64_t  reserved_a           :   1;    //  reserved bits
        uint64_t  CH1_DTW              :   3;    //  see name
        uint64_t  CH1_STW              :   3;    //  see name
        uint64_t  CH1_STAT_DST         :   1;    //  see name
        uint64_t  CH1_STAT_SRC         :   1;    //  see name
        uint64_t  CH1_DST_SCA_EN       :   1;    //  see name
        uint64_t  CH1_SRC_GAT_EN       :   1;    //  see name
        uint64_t  CH1_LOCK_EN          :   1;    //  see name
        uint64_t  CH1_MULTI_BLK_EN     :   1;    //  see name
        uint64_t  CH1_CTL_WB_EN        :   1;    //  see name
        uint64_t  CH1_HC_LLP           :   1;    //  see name
        uint64_t  CH1_FC               :   2;    //  see name
        uint64_t  CH1_MAX_MULT_SIZE    :   3;    //  see name
        uint64_t  CH1_DMS              :   3;    //  see name
        uint64_t  CH1_LMS              :   3;    //  see name
        uint64_t  CH1_SMS              :   3;    //  see name
        uint64_t  CH1_FIFO_DEPTH       :   3;    //  see name
        uint64_t  reserved             :   1;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DMA_COMP_PARAMS_3_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DMA_COMP_PARAMS_2 desc:  Component Parameters Register 3
typedef volatile union {
    struct {
        uint64_t  CH0_DTW              :   3;    //  see name
        uint64_t  CH0_STW              :   3;    //  see name
        uint64_t  CH0_STAT_DST         :   1;    //  see name
        uint64_t  CH0_STAT_SRC         :   1;    //  see name
        uint64_t  CH0_DST_SCA_EN       :   1;    //  see name
        uint64_t  CH0_SRC_GAT_EN       :   1;    //  see name
        uint64_t  CH0_LOCK_EN          :   1;    //  see name
        uint64_t  CH0_MULTI_BLK_EN     :   1;    //  see name
        uint64_t  CH0_CTL_WB_EN        :   1;    //  see name
        uint64_t  CH0_HC_LLP           :   1;    //  see name
        uint64_t  CH0_FC               :   2;    //  see name
        uint64_t  CH0_MAX_MULT_SIZE    :   3;    //  see name
        uint64_t  CH0_DMS              :   3;    //  see name
        uint64_t  CH0_LMS              :   3;    //  see name
        uint64_t  CH0_SMS              :   3;    //  see name
        uint64_t  CH0_FIFO_DEPTH       :   3;    //  see name
        uint64_t  reserved_a           :   1;    //  reserved bits
        uint64_t  CH0_MULTI_BLK_TYPE   :   4;    //  see name
        uint64_t  CH1_MULTI_BLK_TYPE   :   4;    //  see name
        uint64_t  CH2_MULTI_BLK_TYPE   :   4;    //  see name
        uint64_t  CH3_MULTI_BLK_TYPE   :   4;    //  see name
        uint64_t  CH4_MULTI_BLK_TYPE   :   4;    //  see name
        uint64_t  CH5_MULTI_BLK_TYPE   :   4;    //  see name
        uint64_t  CH6_MULTI_BLK_TYPE   :   4;    //  see name
        uint64_t  CH7_MULTI_BLK_TYPE   :   4;    //  see name

    }                                field;
    uint64_t                         val;
} DMA_COMP_PARAMS_2_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DMA_COMP_PARAMS_1 desc:  Component Parameters Register 1
typedef volatile union {
    struct {
        uint64_t  CH0_MAX_BLK_SIZE     :   4;    //  see name
        uint64_t  CH1_MAX_BLK_SIZE     :   4;    //  see name
        uint64_t  CH2_MAX_BLK_SIZE     :   4;    //  see name
        uint64_t  CH3_MAX_BLK_SIZE     :   4;    //  see name
        uint64_t  CH4_MAX_BLK_SIZE     :   4;    //  see name
        uint64_t  CH5_MAX_BLK_SIZE     :   4;    //  see name
        uint64_t  CH6_MAX_BLK_SIZE     :   4;    //  see name
        uint64_t  CH7_MAX_BLK_SIZE     :   4;    //  see name
        uint64_t  BIG_ENDIAN           :   1;    //  see name
        uint64_t  INTR_IO              :   2;    //  see name
        uint64_t  MABRST               :   1;    //  see name
        uint64_t  reserved_a           :   4;    //  reserved bits
        uint64_t  NUM_CHANNELS         :   3;    //  see name
        uint64_t  NUM_MASTER_INT       :   2;    //  see name
        uint64_t  S_HDATA_WIDTH        :   2;    //  see name
        uint64_t  M1_HDATA_WIDTH       :   2;    //  see name
        uint64_t  M2_HDATA_WIDTH       :   2;    //  see name
        uint64_t  M3_HDATA_WIDTH       :   2;    //  see name
        uint64_t  M4_HDATA_WIDTH       :   2;    //  see name
        uint64_t  NUM_HS_INT           :   5;    //  see name
        uint64_t  ADD_ENCODED_PARAMS   :   1;    //  see name
        uint64_t  STATIC_ENDIAN_SELECT :   1;    //  see name
        uint64_t  reserved             :   2;    //  reserved bits

    }                                field;
    uint64_t                         val;
} DMA_COMP_PARAMS_1_t;

// --------------------------------------------------------------------------------------------------------------------------------

// DMA_Component_ID desc:  Component Version ID register
typedef volatile union {
    struct {
        uint64_t  DMA_COMP_TYPE        :  32;    //  Designware release number
        uint64_t  DMA_COMP_VERSION     :  32;    //  Designware release number

    }                                field;
    uint64_t                         val;
} DMA_Component_ID_t;

// --------------------------------------------------------------------------------------------------------------------------------

// starting the array instantiation section
typedef struct {
    SAR0_t                     SAR0;             // offset 4'h0, width 64
    DAR0_t                     DAR0;             // offset 4'h8, width 64
    LLP0_t                     LLP0;             // offset 8'h10, width 64
    CTL0_t                     CTL0;             // offset 8'h18, width 64
    SSTAT0_t                   SSTAT0;           // offset 8'h20, width 64
    DSTAT0_t                   DSTAT0;           // offset 8'h28, width 64
    SSTATAR0_t                 SSTATAR0;         // offset 8'h30, width 64
    DSTATAR0_t                 DSTATAR0;         // offset 8'h38, width 64
    CFG0_t                     CFG0;             // offset 8'h40, width 64
    uint8_t                    rsvd0[16];
    SAR1_t                     SAR1;             // offset 8'h58, width 64
    DAR1_t                     DAR1;             // offset 8'h60, width 64
    LLP1_t                     LLP1;             // offset 8'h68, width 64
    CTL1_t                     CTL1;             // offset 8'h70, width 64
    SSTAT1_t                   SSTAT1;           // offset 8'h78, width 64
    DSTAT1_t                   DSTAT1;           // offset 8'h80, width 64
    SSTATAR1_t                 SSTATAR1;         // offset 8'h88, width 64
    DSTATAR1_t                 DSTATAR1;         // offset 8'h90, width 64
    CFG1_t                     CFG1;             // offset 8'h98, width 64
    uint8_t                    rsvd1[16];
    SAR2_t                     SAR2;             // offset 12'h0B0, width 64
    DAR2_t                     DAR2;             // offset 12'h0B8, width 64
    LLP2_t                     LLP2;             // offset 12'h0C0, width 64
    CTL2_t                     CTL2;             // offset 12'h0C8, width 64
    SSTAT2_t                   SSTAT2;           // offset 12'h0D0, width 64
    DSTAT2_t                   DSTAT2;           // offset 12'h0D8, width 64
    SSTATAR2_t                 SSTATAR2;         // offset 12'h0E0, width 64
    DSTATAR2_t                 DSTATAR2;         // offset 12'h0E8, width 64
    CFG2_t                     CFG2;             // offset 12'h0F0, width 64
    uint8_t                    rsvd2[16];
    SAR3_t                     SAR3;             // offset 12'h108, width 64
    DAR3_t                     DAR3;             // offset 12'h110, width 64
    LLP3_t                     LLP3;             // offset 12'h118, width 64
    CTL3_t                     CTL3;             // offset 12'h120, width 64
    SSTAT3_t                   SSTAT3;           // offset 12'h128, width 64
    DSTAT3_t                   DSTAT3;           // offset 12'h130, width 64
    SSTATAR3_t                 SSTATAR3;         // offset 12'h138, width 64
    DSTATAR3_t                 DSTATAR3;         // offset 12'h140, width 64
    CFG3_t                     CFG3;             // offset 12'h148, width 64
    uint8_t                    rsvd3[368];
    RawTfr_t                   RawTfr;           // offset 12'h2C0, width 64
    RawBlock_t                 RawBlock;         // offset 12'h2C8, width 64
    RawSrcTran_t               RawSrcTran;       // offset 12'h2D0, width 64
    RawDstTran_t               RawDstTran;       // offset 12'h2D8, width 64
    RawErr_t                   RawErr;           // offset 12'h2E0, width 64
    StatusTfr_t                StatusTfr;        // offset 12'h2E8, width 64
    StatusBlock_t              StatusBlock;      // offset 12'h2F0, width 64
    StatusSrcTran_t            StatusSrcTran;    // offset 12'h2F8, width 64
    StatusDstTran_t            StatusDstTran;    // offset 12'h300, width 64
    StatusErr_t                StatusErr;        // offset 12'h308, width 64
    MaskTfr_t                  MaskTfr;          // offset 12'h310, width 64
    MaskBlock_t                MaskBlock;        // offset 12'h318, width 64
    MaskSrcTran_t              MaskSrcTran;      // offset 12'h320, width 64
    MaskDstTran_t              MaskDstTran;      // offset 12'h328, width 64
    MaskErr_t                  MaskErr;          // offset 12'h330, width 64
    ClearTfr_t                 ClearTfr;         // offset 12'h338, width 64
    ClearBlock_t               ClearBlock;       // offset 12'h340, width 64
    ClearSrcTran_t             ClearSrcTran;     // offset 12'h348, width 64
    ClearDstTran_t             ClearDstTran;     // offset 12'h350, width 64
    ClearErr_t                 ClearErr;         // offset 12'h358, width 64
    Statusint_t                Statusint;        // offset 12'h360, width 64
    ReqSrcReg_t                ReqSrcReg;        // offset 12'h368, width 64
    ReqDstReg_t                ReqDstReg;        // offset 12'h370, width 64
    SglReqSrcReg_t             SglReqSrcReg;     // offset 12'h378, width 64
    SglReqDstReg_t             SglReqDstReg;     // offset 12'h380, width 64
    LastSrcReg_t               LastSrcReg;       // offset 12'h388, width 64
    LastDstReg_t               LastDstReg;       // offset 12'h390, width 64
    DmaCfgReg_t                DmaCfgReg;        // offset 12'h398, width 64
    ChEnReg_t                  ChEnReg;          // offset 12'h3A0, width 64
    DmaIdReg_t                 DmaIdReg;         // offset 12'h3A8, width 64
    DmaTestReg_t               DmaTestReg;       // offset 12'h3B0, width 64
    uint8_t                    rsvd4[16];
    DMA_COMP_PARAMS_6_t        DMA_COMP_PARAMS_6; // offset 12'h3C8, width 64
    DMA_COMP_PARAMS_5_t        DMA_COMP_PARAMS_5; // offset 12'h3D0, width 64
    DMA_COMP_PARAMS_4_t        DMA_COMP_PARAMS_4; // offset 12'h3D8, width 64
    DMA_COMP_PARAMS_3_t        DMA_COMP_PARAMS_3; // offset 12'h3E0, width 64
    DMA_COMP_PARAMS_2_t        DMA_COMP_PARAMS_2; // offset 12'h3E8, width 64
    DMA_COMP_PARAMS_1_t        DMA_COMP_PARAMS_1; // offset 12'h3F0, width 64
    DMA_Component_ID_t         DMA_Component_ID; // offset 12'h3F8, width 64
} DW_dmac_t;                                     // size:  12'h400
